nCompany:nnQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAnn## Job Area:nnEngineering Group, Engineering Group u003e ASICS EngineeringnnGeneral Summary:nnJob Summary:nn * As a member of the Qualcomm Standard Cell Design team, the candidate will be responsible for contributing to the development of high-quality intellectual property (IP) for advanced semiconductor technology nodes. This role involves applying strong technical expertise and creativity to deliver efficient and scalable physical layout designs within Qualcommu2019s structured and methodical design framework. The position offers significant opportunities for professional and engineering growth through exposure to industry-leading design practices and cutting-edge technologiesnnnnJob description:nn * Design and develop physical layouts for logic standard cells using industry-standard computer-aided design (CAD) tools, such as Cadence Virtuoso. This role involves leveraging scripting and algorithmic programming languages, including SKILL and Python, to support layout automation, optimization,



and design efficiency.n * Perform comprehensive layout verification, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC).n * Collaborate closely with circuit designers to ensure layouts meet quality, performance, and reliability requirements.n * Maintain and manage layout databases using designated Design Management software.n * Engage with the engineering design team to understand design concepts, constraints, and project milestones; accurately and concisely communicate design status and track schedules.n * Proactively and independently identify and resolve design- and PDK-related issues; clearly document and communicate solutions to layout and engineering stakeholders.n * Work closely with Circuit Designers and Mask Layout Designers across integral development sites, including the United States, Taiwan, and India.n * Demonstra

📌 Standard Cell Layout Engineer (México)
🏢 Qualcomm
📍 México