Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Bachelor's Degree or higher in Electrical Engineering, Computer Engineering, or related fields. Cadence Synopsys Mentor Ansys Python, C++, TCL, Perl, Awk Verilog/VHDL,Unix/Linux Excellent written and verbal communication. Automation with Perl, Python and tcl is plus Provide technical leadership and direction to project execution. Manage project timelines, deliverables and track them to closure. Mentor, guide and help team members in a fast-paced environment. Collaborate with design team and work with cross functional teams. Use good verbal and written communication skills to describe daily technical and non-technical issues Take responsibility for your own work and making decisions Exercise creativity to troubleshoot technical problems

📌 Physical Design Engineer (México)
🏢 Qualcomm
📍 México