Semiconductor Engineering seeks a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, directed and constrained-random test content, coverage closure, and debug across block, subsystem, and SoC levels.
You’ll collaborate with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.
📌 SoC Verification Engineer: UVM Testbenches, Coverage Lead (Costa Rica)
🏢 Semiconductor Engineering
📍 Costa Rica
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