Micron Technology, Inc. seeks a DRAM Design Engineer to translate schematics into DRAM IP layouts and drive physical verification for multiple projects. You will coordinate with general teams and guide junior designers to meet tight deadlines.
You will apply Cadence Virtuoso and Mentor Calibre tools, optimize layouts for performance, area and yield, and contribute to continuous improvement in layout methodologies. Based in Mexico, this role emphasizes collaboration and technical leadership.
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📌 DRAM Design Layout Engineer – Design Tech Lead (Jalisco)
🏢 Micron
📍 Jalisco
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