Micron Technology, Inc. in Guadalajara, Mexico, is seeking a Layout Design Engineer to advance analog/mixed-signal layouts for high‑performance memory technologies. You will collaborate with general teams on multiple projects, delivering high-quality layouts on schedule.
The role requires hands-on experience with Cadence VLE/VXL and Mentor Calibre, and a BE or MTech in Electronic/VLSI Engineering with 5+ years of layout expertise in CMOS technologies.