SOC Design Verification Engineer- Pre-si/post-si Verification (Tijuana)

SOC Design Verification Engineer- Pre-si/post-si Verification (Tijuana)

20 ago
|
Qualcomm
|
Tijuana

20 ago

Qualcomm

Tijuana

Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:
Job Overview

Key Responsibilities - Pre-Si and Post-Si Verification:
- Develop and execute verification plans for SoC, subsystem, and IP-level features across pre-silicon and post-silicon phases.
- Build, enhance, and maintain SystemVerilog/UVM, C/C++, processor-based, emulation, and acceleration verification environments.
- Create directed, constrained-random, stress, performance, power, and system-level test scenarios to validate architecture and real-use-case behavior.
- Develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics for verification closure.
- Debug RTL, testbench, emulation, firmware, ATE/vector, and silicon bring-up issues using logs, waveforms, traces, and hardware debug data.
- Support post-silicon validation, silicon characterization, ATE pattern debug, failure triage, and correlation between simulation, emulation, and silicon results.
- Drive coverage closure,



regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.
- Participate in architecture, micro-architecture, design, validation, and test-plan reviews to ensure verification and bring-up requirements are captured early.
- Verify complex SoC features including multi-core CPU systems, cache coherency and interconnect fabrics, DDR/HBM memory subsystems, PCIe/CXL/Ethernet/high-speed interfaces, security, performance, and power-management features.
- For Engineer level: execute assigned verification tasks, develop tests and checkers, debug failures, maintain regressions, and contribute to coverage and bring-up activities.
- For Senior Engineer level: own feature/subsystem verification from plan to closure, lead debug across teams, mentor engineers, identify schedule and quality risks, and drive methodology/automation improvements.
- Contribu

📌 SOC Design Verification Engineer- Pre-si/post-si Verification (Tijuana)
🏢 Qualcomm
📍 Tijuana

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