Define system-level power management architecture and operating modes
Define reset flow architecture, including cold and warm reset sequencing and reset-power state interactions
Define hardware–firmware power management interfaces and compliance expectations
Define power management requirements and constraints to guide implementation teams
Align architecture, RTL, physical design, thermal, and firmware teams around a coherent PM strategy
7+ years in SoC or CPU power management architecture
~ Direct experience with ARM CPU power management architecture, including familiarity with ARM power management specifications and compliance requirements (e.g., Strong understanding of system-level power state management and hardware–firmware PM interaction
~ Track record of cross-functional coordination across architecture, design, and firmware teams
Understanding of thermal management concepts and power-thermal interaction at system level
High-performance or server-class CPU experience
Multi-generation architecture planning experience
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📌 Power Management Architect (Ciudad de México)
🏢 AheadComputing
📍 Ciudad de México