Project description:
- working for a general provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. a leader in light management technologies for 3 d sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications -. Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers
.
responsibiliti
- es: we are seeking a principal/staff-level fpga engineer — a recognized technical authority — to own fpga architecture for our state-of-the-art communications test & measurement produ - cts. The successful candidate will define and drive end-to-end fpga architecture, including make/buy tradeoffs on ip, floorplanning and timing closure strategy for multi-gigabit designs, and dfx approach, using verilog/system verilog/vhdl and industry-leading simulation, synthesis, place-and-route, and formal/uvm verification tools. This person will serve as the final technical escalation point for fpga design and debug issues across the team, mentor other fpga engineers, and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewh
ere.
mandatory s
- kill - s: f
pgavhdl
mandatory skills des
- cription: bs or ms degree in electrical and/or computer engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-gbps ser des/transceiver-based fpg - a designs. Demonstrated expertise architecting and implementing high-speed fpga designs using verilog/system verilog and/or vhdl - required. Deep, hands-on expertise with fpga transceivers, hard ip,



and plls — including timing closure, equalization, and link debug at multi-gbps rates — required (not incidental - exposure). Demonstrated experience closing timing and debugging link-layer issues on high-speed ethernet (10 m to 1.6 t) and ip protocol stacks in productio - n designs. Proven expertise with optical interfaces and modules (sfps, qsfps) in shipped - products. Deep working knowledge of vlans, mpls, vpls, and voice/video over ip (vo - ip, iptv). Extensive experience with amd or altera fpga devices and their full implementation toolchains, including advanced timing closure and floorplanning t - echniques. Proven experience with formal verification and/or uvm-based verification methodologies, not limited to directed te - stbenches. Demonstrated track record of taking fpga designs from architecture through volume production, including systems-level tradeoffs across the hw/fw - boundary. Version control experience using git or simi - lar tools. Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across - the world. Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product en
vironment.
nice-to-have skills
- description: patents or published work in fpga architecture, high-speed digital de - sign, or dsp. Experience defining test strategies for multi-gbps compliance testing (particularly relevant for t&m; product - development). General purpose microprocessor and dsp systems, pcie, high-speed digital board design, pll design, and analog signal conditionin - g experience. Simulation experience using siemens questa, aldec riviera, or s - imilar tools. Contribution to or deep familiarity with open verification methodologies (e.g., cocotb, uvm community co - ntributions). Utilization of generative ai tools to assist in concept and implementation of

📌 Field-programmable gate arrays engineer (Ciudad de México)
🏢 Luxoft
📍 Ciudad de México