Company
QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
SoC Design & Synthesis Engineer
Role Description
This role focuses on synthesizing large‐scale SoC RTL designs into high‐quality gate‐level netlists that are ready for Place & Route. Responsibilities include owning all synthesis inputs, executing multi‐stage synthesis flows, and ensuring netlist quality with respect to timing, power, and DFT requirements prior to Physical Design handoff.
The role also contributes to PPA (Power, Performance, Area) optimization by analyzing trade‐offs and recommending design or constraint improvements, while working closely with Design, DFT, and Physical Design teams to resolve issues early in the flow. In addition, the engineer supports functional ECOs and validates post‐change correctness to improve functionality and fix late‐stage issues, ensuring timely delivery of robust, manufacturable designs used in Snapdragon products across mobile, automotive, and edge AI platforms.
Required Skills




- Strong understanding of RTL‐to‐gate synthesis for large SoC designs
- Experience with gate‐level netlist quality checks and PD‐ready handoffs
- Solid knowledge of timing constraints (SDC) across functional and test modes
- Ability to analyze and optimize PPA (Power, Performance, Area) trade‐offs
- Experience supporting or implementing functional ECOs and validating correctness
- Effective debugging, analytical thinking, and execution under tight project schedules

Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.

Preferred Qualifications
- Master's degree in

📌 SoC Design (Tijuana)
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