This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SoCs (Systems on Chip). Main responsibilities include defining and executing test methodologies and characterization of high-speed SERDES interfaces such as PCIe, USB3, UFS, DP, MIPI (DSI, CSI), PLLs, and advanced LP-DDR & PC-DDR subsystem components, including DRAM, DRAM controllers, mixed-signal PHY IPs, IOs, clocking architecture, delay circuits, and power distribution networks.
The role involves developing and executing characterization plans for high-speed interfaces to optimize design parameters and validate electrical compliance. Responsibilities also include first-silicon bring-up and debug, qualification of designs fabricated at external foundries, and technical data analysis of parametric performance across different operating conditions and configurations.
The engineer will assist in hardware design and troubleshooting of Power Integrity (PI) and Signal Integrity (SI) issues related to package and board design. Close collaboration with IC Design, Systems Engineering,



Customer Engineering, and Hardware Applications teams is required to support chip bring-up, debugging, customer issue resolution, and RMA investigations in time-critical environments.
The idóneo candidate is passionate about delivering high-quality results, continuously learning about new technologies and products, staying informed on industry trends and competitor solutions, and supporting specialized engineering analyses such as feasibility studies, signal integrity investigations, and teardown analyses.
Preferred Qualifications
- Fluent English communication skills (>95% verbal and written).
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Fresh graduates are encouraged to apply.
- Strong understanding of VLSI technologies, CMOS analog and digital integrated circuits, mixed-signal design, and semiconductor physics.
- Knowledge of high-speed testi

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