Formal Verification Engineer (Guadalajara)

Formal Verification Engineer (Guadalajara)

12 ago
|
AheadComputing
|
Guadalajara

12 ago

AheadComputing

Guadalajara

We are seeking a Formal Verification Engineer to join our team. In this role, you will leverage advanced formal verification techniques to ensure the correctness and performance of high-end RISC‑V cores. You will collaborate closely with architects and RTL engineers, employing cutting‑edge formal tools and methodologies to build innovative verification solutions. This position offers a unique opportunity to shape the development of high‑quality CPU designs and optimize the CPU verification process through rigorous formal analysis and bug detection methods.

Responsibilities
- Engage in formal verification of architecture and microarchitecture for high‑performance RISC‑V core.
- Collaborate with architects and RTL design engineers to identify, specify, and verify components suitable for formal analysis.
- Use formal tools and methodologies focused on ensuring the correctness of arithmetic, logical, and data transfer operations.
- Develop formal abstract models to verify system‑level properties such as deadlock freedom and non‑starvation.
- Create innovative verification flows,



integrating formal techniques with simulation‑based methods for effective bug detection.
- Build reusable and scalable proof techniques to enhance the formal verification process.

Qualifications & Skills
- Bachelor’s (BS) or Master’s (MS) degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
- Hands‑on experience with data path and control path formal techniques.
- Familiarity with model checking tools for formal verification.
- Strong problem‑solving skills with excellent written and verbal communication abilities.
- Exceptional organizational skills and high self‑motivation.
- Proven ability to collaborate effectively with diverse design teams.
- Exceptional problem‑solving skills with the ability to identify and troubleshoot complex CPU design issues.
- Familiarity with UVM (Universal Verification Methodology) or similar frameworks.
- Strong understan

📌 Formal Verification Engineer (Guadalajara)
🏢 AheadComputing
📍 Guadalajara

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