CompanyQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Job AreaEngineering Group, Engineering Group > Hardware Engineering
General SummaryThis position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip). Main responsibilities include defining and executing the development of test methodologies and characterization of high‑speed SERDES interfaces such as PCIe, USB3, UFS, DP, MIPI (DSI, CSI), PLLs, and leading‑edge LP‑DDR & PC‑DDR subsystem components (DRAM, DRAM controller, mixed‑signal PHY IP, I/Os, clocking architecture, delay circuits, power distribution network) as well as other proprietary interfaces. Responsibilities include developing and executing characterization plans for high‑speed interfaces to optimize design parameters and validate electrical compliance, driving corresponding first‑silicon bring‑up & debug to qualify designs fabricated at external foundries, and performing technical data analysis of parametric performance over various operating conditions and configurations.



The engineer will also assist in HW design and debug power integrity (PI) and signal integrity (SI) issues related to package and board design. The engineer will work closely with cross‑functional teams such as IC design, systems engineering for chip/circuit bring‑up and debug, and with customer engineering and hardware applications teams to resolve customer issues/RMA debug in a time‑critical environment. The individual selected for the position should be passionate about delivering quality work products, seek to continually learn about new products, and possess essential knowledge of industry trends, competitor products, and advances in various engineering fields from publicly available information, assisting in conducting specialized analyses (e.g., feasibility studies, signal integrity, teardown analyses).
Minimum Qualifications
- Bachelor’s degree in Computer Science, Electrical/Electronics Enginee

📌 HSIO/DDR Bench Test Engineer (Tijuana)
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