Pathfinding Senior Design Layout Engineer Tlaquepaque, Jalisco, Mexico Posted a day ago (San Pedro Tlaquepaque)

Pathfinding Senior Design Layout Engineer Tlaquepaque, Jalisco, Mexico Posted a day ago (San Pedro Tlaquepaque)

12 ago
|
Micron Technology
|
San Pedro Tlaquepaque

12 ago

Micron Technology

San Pedro Tlaquepaque

Pathfinding Senior Design Layout EngineerTlaquepaque, Jalisco, MexicoApply NowFind out how well you match with this jobJob IDJR93766Our vision is to transform how the world uses information to enrich life for *all*.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Job DescriptionFor more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists developing groundbreaking technologies that transform how the world uses information to enrich life.We are seeking a Layout Design Engineer to join Micron’s DDR Team in Guadalajara, Mexico. In this role, you will collaborate with integral teams in a multi‐project environment to deliver high‐quality layout design solutions across analog, mixed‐signal, and custom digital domains.Responsibilities* Design and develop critical analog, mixed‐signal,



custom digital blocks, and support full‐chip level integration.* Perform layout verification activities including LVS, DRC, antenna checks, quality reviews, and documentation.* Ensure on‐time delivery of block‐level layouts that meet quality expectations.* Lead planning, area/time estimation, scheduling, delegation, and execution across multiple concurrent projects.* Mentor and guide developing team members during sub-block layout execution and review their work.* Communicate effectively with global engineering teams to ensure layout project success.Minimum Qualifications* Demonstrated ability in analog/custom layout design in advanced CMOS processes across various technology nodes (Planar, FinFET).* Bachelor’s, Master’s, or equivalent experience in Electronics, VLSI Engineering, or a related field.* Expertise with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.* Hands‐on experience cre

📌 Pathfinding Senior Design Layout Engineer Tlaquepaque, Jalisco, Mexico Posted a day ago (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque

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