North American Production Sharing, Inc. seeks an ASIC design engineer to synthesize large-scale SoC RTL into gate-level netlists and own multi-stage synthesis flows, ensuring PD handoff readiness.
You will optimize PPA, analyze timing constraints (SDC), and support functional ECOs while collaborating with Design, DFT, and Physical Design teams to deliver robust, manufacturable Snapdragon-class designs.
Frontend experience in ASIC design and strong debugging, scripting, and execution under tight
#J-*****-Ljbffr
📌 Soc Synthesis & Ppa Optimization Engineer (Tijuana)
🏢 North American Production Sharing
📍 Tijuana
Postulate a este anuncio
Muestra tus habilidades a la empresa, rellenar el formulario y deja un toque personal en la carta, ayudará el reclutador en la elección del candidato.