we are seeking a principal/staff-level fpga engineer and technical authority to own the end-to-end fpga architecture for our next-generation communications test & measurement products.

in this role, you will drive critical architectural decisions—from make/buy ip tradeoffs to floorplanning and timing closure strategies for multi-gigabit designs. As the final technical escalation point, you will mentor engineers, lead complex debug efforts, and guide products from architecture all the way through volume production.

key responsibilities

- architectural ownership: define and drive end-to-end fpga architecture, including dfx approaches and ip evaluation.
- high-speed design & timing: own floorplanning, multi-gigabit transceiver integration, and advanced timing closure strategies for complex designs.
- technical leadership & escalation: serve as the ultimate technical authority for fpga design, acting as the primary escalation point for team debug issues.
- bring-up & root cause analysis: lead hands-on root-cause debug for silicon, board bring-up, and link-layer issues across high-speed protocols.
- mentorship: elevate the engineering team by mentoring peers and communicating high-level architecture decisions to general stakeholders.

what you'll bring (mandatory requirements)

- education & experience:



bs or ms in electrical/computer engineering with 12–15+ years of relevant experience, including 5+ years specifically architecting and closing timing on multi-gbps serdes/transceiver-based designs.
- hdl mastery: demonstrated expertise implementing high-speed designs using verilog, systemverilog, and/or vhdl.
- transceiver expertise: deep, hands-on experience with fpga transceivers, hard ip, plls, equalization, and multi-gbps link debug.
- networking & protocols: proven experience with high-speed ethernet (10m to 1.6t), ip protocol stacks, optical interfaces (sfps, qsfps), vlans, mpls, vpls, and voip/iptv.
- toolchain & device mastery: extensive production experience with amd or altera devices and their full implementation toolchains (advanced floorplanning and timing closure).
- advanced verification: proven background in formal verification and/or uvm-based verification methodologies.
- product lifecycle: track record of taking complex fpga designs from architecture through volume production, including hw/fw boundary tradeoffs.
- communication: exceptional written and verbal communication skills with a proven ability to mentor and lead globally distributed teams.

📌 Principal / staff fpga engineer — communications test & measurement (México)
🏢 Luxoft
📍 México