Senior Engineer – Verification Enablement Position ID: JR101078 in the Scribe Design Group of the Research and Development (R&D;) department.
We are a team driving innovation in advanced technology development through scribe test structure design, layout, and validation. As a Scribe Design Verification Enablement Engineer you will support development and validation of advanced process technology through verification flow enablement for scribe test structure design and layout, CAD, and reticle creation.
Responsibilities Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory, Logic and Analog circuits
Parasitic modeling and assisting in design validation, reticle experiments and required tape‑out revisions
Overseeing and managing the layout process including floor‑planning, placement, and routing
Performing verification processes with modeling and simulation using industry standard simulators
Contributing to cross‑group communication to work towards standardization and group success
Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product
Proactively soliciting guidance from Standards, CAD, modeling, and verification groups to improve the design quality
Driving innovation into future Memory generations within a dynamic work environment
Minimum Qualifications Master’s or higher degree in Electrical/Electronics Engineering or related field.




5‑8 years of relevant experience in IC design flow development, Memory/Mixed‑Signal Design and Layout.
Understanding of front‑end, back‑end analog and mixed signal design flows and methodologies.
Knowledge of SPICE simulators such as HSPICE and Finesim, and hands‑on experience with schematic entry, netlist extraction, and post‑layout verification.
Familiarity with semiconductor electrical fundamentals and device physics.
Capable of working in a multi‑functional and multi‑site team environment spanning multiple time zones.
Experience in automation of IC design flows using SKILL, Perl, Python, Bash, C‑Shell coding.
Preferred Qualifications Understanding of physical verification flows like LVS, DRC, PEX and rule‑deck coding using Calibre SVRF/TVF.
Knowledge of machine learning algorithms and methodologies.
Experience in maintaining intranet portals such as Confluence and SharePoint.
Knowledge of Microsoft PowerBI tool.
Benefits Micron offers a range of medical, dental and vision plans, income protection, paid family leave, paid time‑off and holidays, and other benefits to support wellbeing and professional growth.
EEO Statement Micron is a proud equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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📌 Senior Engineer - Verification Enablement, Test Structure Design and Layout (Centro)
🏢 Micron Technology
📍 Centro