You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.
- Responsible for Spice simulations (Hspice/Primesim/Finesim/AFS/Spectre) for PVT corners validation and STA vs spice correlation. Timing package validation across advanced process technologies using PT/PT-SI and Tempus.
- You will facilitate and drive STA methodology using PT-SI, Tempus and best in class timing ECO tools. Work on timing sign off specification for different projects and support timing sign off for complex SOC’s. Hands on contribution for STA timing sign off.
- A timing Engineer should be able to understand all kind of intricate timing paths (digital, analog, mixed signal),



timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/FC/Genus/Oasis, ICC2/FusionCompiler/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus.
- You should have good execution knowledge.
- Your contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from pdk to vlsi design production.
- You should have good programming skills Python, Perl, TCL, Unix shell, C/C++.
- ML modeling experience is a plus

📌 Timing and Technology Engineer (Tijuana)
🏢 North American Production Sharing
📍 Tijuana