Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:We are seeking motivated Engineer and Senior Engineer candidates to join our Pre‐Silicon and Post‐Silicon SoC Verification team.
In this role, you will verify next‐generation SoCs that power Mobile, AI, high‐performance computing, and cloud infrastructure products.
The position spans pre‐silicon simulation, emulation, acceleration, and post‐silicon bring‐up/validation activities, with responsibilities aligned to the candidate's experience level.Key Responsibilities – Pre‐Si and Post‐Si Verification:Develop and execute verification plans for SoC, subsystem, and IP‐level features across pre‐silicon and post‐silicon phases.Build, enhance, and maintain SystemVerilog/UVM, C/C++, processor‐based, emulation, and acceleration verification environments.Create directed, constrained‐random, stress, performance, power, and system‐level test scenarios to validate architecture and real‐use‐case behavior.Develop assertions, functional coverage models, checkers, scoreboards, and sign‐off metrics for verification closure.Debug RTL, testbench, emulation, firmware, ATE/vector, and silicon bring‐up issues using logs, waveforms, traces, and hardware debug data.Support post‐silicon validation, silicon characterization, ATE pattern debug, failure triage, and correlation between simulation, emulation, and silicon results.Drive coverage closure, regression health, bug tracking, and verification sign‐off using functional, code, assertion, and scenario coverage metrics.Participate in architecture, micro‐architecture, design, validation, and test‐plan reviews to ensure verification and bring‐up requirements are captured early.Verify complex SoC features including multi‐core CPU systems, cache coherency and interconnect fabrics, DDR/HBM memory subsystems, PCIe/CXL/Ethernet/high‐speed interfaces, security, performance, and power‐management features.For Engineer level: execute assigned verification tasks, develop tests and checkers, debug failures, maintain regressions, and contribute to coverage and bring‐up activities.For Senior Engineer level: own feature/subsystem verification from plan to closure,



lead debug across teams, mentor engineers, identify schedule and quality risks, and drive methodology/automation improvements.Contribute to reusable verification components, scripting automation, AI‐assisted verification workflows, and continuous improvement of pre‐silicon and post‐silicon validation processes.Minimum Qualifications:Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.PhD in Science, Engineering, or related field.Strong knowledge of System Verilog, UVM, C/C++, assertion‐based verification, coverage‐driven verification, and system‐level use‐case verification.Experience developing or using verification environments from architecture/specification through sign‐off, including regression, coverage, and debug flows.Understanding of post‐silicon validation concepts such as bring‐up, ATE/vector debug, silicon failure triage, hardware/software interaction, or correlation with pre‐silicon results.Strong understanding of computer architecture, digital design fundamentals, and SoC integration concepts.Excellent communication, collaboration, ownership, and problem‐solving skills.Engineer: typically 2+ years of relevant design verification, validation, or SoC debug experience.Senior Engineer: typically 4+ years of relevant experience with demonstrated ownership of complex verification, validation, or silicon bring‐up deliverables.Preferred Qualifications:Experience with one or more of the following pre‐silicon or post‐silicon domains: CPU, subsystem, or full‐chip SoC verification.Cache coherency protocols such as ACE, CHI, or CXL.DDR, LPDDR, or HBM memory subsystems.PCIe, CXL, Ethernet, networking,



or high‐speed interface verification.AI/ML accelerator, security, RAS, performance, or power feature verification.Post‐silicon bring‐up, silicon validation, ATE pattern debug, shmoo/debug analysis, or silicon failure triage.Experience with emulation/acceleration platforms such as Veloce, Palladium, or ZeBu, and correlation between simulation, emulation, and silicon results.Silicon validation (Debug using Trace32) experience is preferred.Experience with Portable Stimulus, formal verification, power‐aware verification, firmware‐driven validation, or hardware/software co‐verification.Proficiency in Python, Perl, shell scripting, or other automation languages for regression, debug, data analysis, and productivity improvements.For Senior Engineer candidates: demonstrated ability to lead feature closure, coordinate across design/validation/test/software teams, mentor engineers, and communicate technical risks to stakeholders.Preferred Candidate Profile:The adecuado candidate is a hands‐on verification engineer who is passionate about solving complex technical challenges and delivering high‐quality silicon.
They should possess strong debugging skills, a solid understanding of SoC architecture, and the ability to thrive in a fast‐paced, collaborative environment.Equal Opportunity Employer Statement:Qualcomm is an equal opportunity employer.
If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process.
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Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
Qualcomm is also committed to making our workplace accessible for individuals with disabilities.Legal Disclaimer:Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information to the extent those requirements are permissible under applicable law.
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📌 Soc Design Verification Engineer, Staff– Pre-Si/Post-Si Verification (Tijuana)
🏢 Qualcomm
📍 Tijuana