CompanyQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAResponsibilitiesWork with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologies 5nm, 4nm ... 2nm and beyond.Responsible for Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation and STA sign off using PT/PT-SI and Tempus.Responsible for block level PPA analysis/implementation (RTL to GDS flow) for hard macros using FC Synthesis, FC Place and Route, Genus and Innovus.Responsible for design implementation of multiple blocks working with foundry DTCO team, EDA companies (partners), CAD team and IP team driving Fmax optimization, PPAY and cost improvements/reduction.Good execution knowledge.Contribution should improve design convergence process across the company, design PPAY and support new advanced process technologies bring-up in production from PDK to VLSI design.Good programming skills in Python, Perl, TCL, Unix shell, C/C++.
ML modeling experience is a plus.Minimum QualificationsBachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration,



or related work experience.Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.PhD in Science, Engineering, or related field.Equal Opportunity EmployerQualcomm is an equal opportunity employer.
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You may e‐mail disability‐ or call Qualcomm's toll‐free number.
Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process.
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📌 Asic Dtco, Timing And Technology Engineer (Tijuana)
🏢 Qualcomm
📍 Tijuana