Overview

This position requires candidates to upload an English resume. An English resume is required to be considered for this position.

Responsibilities

- Perform functional logic verification of an integrated SoC to ensure design meets specifications.
- Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
- Execute verification plans and define and run emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
- Replicate, root cause, and debug issues in the pre‑silicon environment.
- Find and implement corrective measures to resolve failing tests.
- Collaborate and communicate with SoC architects, microarchitects, full chip architects, RTL developers, post‑silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
- Document test plans and drive technical reviews of plans and proofs with design and architecture teams.
- Incorporate and execute security activities within test plans, including regression and debug tests, to ensure security coverage.
- Maintain and improve existing functional verification infrastructure and methodology.
- Absorb learning from post‑silicon on the quality of validation done during pre‑silicon development, update test plans for missing coverages, and proliferate to future products.

Behavioral Traits

- Collaborating within cross‑functional teams to resolve complex technical challenges.
- Analytical and problem‑solving skills with attention to detail.




- Communicate technical concepts effectively to diverse audiences.
- Very good logical thinking, ability to prioritize work and multi‑tasking.

Minimum Qualifications

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field.
- 6+ months of experience in industry‑standard verification methodologies such as UVM or SystemVerilog or digital design.
- Advance English level.
- Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred Qualifications

- 3+ years SystemVerilog and UVM experience.
- 2+ years in Python for test automation.
- Experience with simulation tools (VCS, Xcelium, Questa).
- ARM‑based SoC or equivalent architectures.
- Pre‑silicon verification experience.
- Memory subsystems, cache coherency, power management.
- AMBA protocols (AXI, AHB, APB) and interconnects.
- C/C++ and scripting proficiency (Perl, Tcl, Shell).
- Formal verification tools and coverage analysis.
- Constrained random and assertion‑based verification.
- Linux/Unix and version control (Git, Perforce).
- Regression testing and CI/CD pipelines.
- Security verification methodologies.
- Experience in some or all aspects of pre‑silicon functional verification, including planning, debug, testbench design,



UPF and coverage closure.

Additional Information

Job Type: College Grad. Shift: Shift 1 (Mexico). Primary Location: Mexico, Guadalajara. Additional Locations: Business group: At the Data Center Group (DCG), we are committed to delivering exceptional products and delighting our customers.

A candidate who accepts an offer of employment in Mexico is required to present their own personal identification information and numbers for the following: Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Additional Notes

Position of Trust: N/A. Work Model for this Role: This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change. Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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📌 SoC Pre-Silicon Verification Engineer (Centro)
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