We are looking for a senior analog layout engineer.
- Layout and abstract design, physical topologies and design methodologies- Verifying and completing the IC with DRC/LVS checks, chip-finishing and bonding.
- Participating in physical design reviews- Delivering back-annotated data needed for timing verification of modules, both standalone and embedded in top level circuitry.
- Properly tagging of IC layout data bases- Work with other team members to build up design knowledge and improve way of working;- Develop his/her leadership on his/her domain of skills and actions- MSEE or BSEE- Minimum of 5 years (10 years for BSEE) experience for analog layout design- Familiar with Cadence back-end design tools: Virtuoso etc.- Familiar with Calibre- Familiar with Skill,



Pearl and other script languages- Familiar with CMOS, BCD processes and p ower management products layout design- Able to establish good relationships with a multi-disciplinary development team, international customers and subcontractors- Creative thinker with helicopter view, capable of finding an appropriate solution to complex problems- Good communicator in both oral and written English- Team player, able to work in a cross-functional-team environmentLI-FCC3More information about NXP in Mexico...LI-fcc3

📌 Senior Layout Engineer (Guadalajara)
🏢 Nxp Semiconductors
📍 Guadalajara