Contribute to innovative memory designs impacting DRAM, NAND, and new technologies. Provide day-to-day support for CAD tools, flows, and collateral, ensuring they meet the needs of DRAM design teams at the Guadalajara DEG Design Center. Collaborate closely with DRAM design, layout, and verification methodology teams to propose and co-develop advanced capabilities, ensuring the deployment of outstanding practices and methodologies. Support all aspects of mixed-signal, transistor-level custom IC design, including logical design, custom layout, parameterized cells, automated place and route tools, physical design verification, ERC, Layout Parasitic Extraction, pre and post layout netlisting and simulation, digital and analog circuit simulation, timing and power analysis, reliability simulation and analysis, tape out, and mask generation.



Apply now and help us craft the future of memory solutions! Bachelor's or preferably a Master's/PhD in Computer Engineering, Computer Science, or Electrical Engineering. *****+ years of direct CAD or Design experience in mixed-signal, custom IC design flows. Proven experience working in highly technical IC Design or CAD teams distributed worldwide. Familiarity with memory design (DDR3/4/5, LP3/4/5, HBM, NAND). Experience qualifying vendor tools and internally developed software releases. Proven ability to develop software prototypes for innovative ideas in IC design, layout, and analysis. Experience running agile (software) sprints. Experience with Machine Learning algorithms and applications, and delivering production-grade ML applications in IC Design.

📌 Senior/Principal Engineer, Memory Cad, Guadalajara (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque