Responsibilities will include, but are not limited to: - Master's degree in Electrical, Computer, or Microelectronic Engineering - Hands-on experience with EDA tools (Cadence Virtuoso Layout and Schematic Editor, Calibre). - Strong circuit design, layout, schematic, and verification skills including DRC, LVS, and circuit simulation (HSPICE). - Strong knowledge of semiconductor device physics, operation, parametric testing, and DFM. - Familiarity with memory array design architectures, fab processes, and failure modes. - Ability to interpret DUT definitions and deliver completed TEGs. - Willingness to learn new skills and explore unfamiliar concepts. - Ability to drive decisions through data and metrics - Proficiency in Perl, Skill code, and UNIX shell scripting languages. - Experience in design debug based on silicon learning. - Advanced knowledge of silicon processes, mask development and OPC processes. "The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited.



The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position." We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

📌 New College Grad - Memory Cell Test Structure Design And Layout (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque