Responsibilities will include, but are not limited to: Support process development activities through memory cell-based test structure solutions by actively engaging with Process Integration, Product and Die Design, Electrical Characterization, Advanced Mask Development and Design Rule teams. Implement novel solutions as the need arises to study the failure mechanisms and to monitor the health of silicon. Assist with parametric correlation and debug to ensure design accuracy. Bachelor of Science in Electrical or Microelectronic Engineering with 5 years of experience, Hands-on experience and proficiency in EDA tools such as Cadence Virtuoso Layout and Schematic Editor, and Calibre. Excellent circuit design, layout, schematic, and verification skills including DRC, LVS, and circuit simulation (hspice). Excellent knowledge of semiconductor device physics, operation, parametric testing, and Design for Manufacturability (DFM). Good knowledge of DRAM and NAND Memory Array design architectures, Fab processes, and failure modes A integral mindset to seamlessly work across cultures and a sense of ownership to independently drive improvements on department level projects. Master of Science in Electrical or Microelectronic Engineering with 3 years of experience. Proficiency in Perl, Skill code, and UNIX shell scripting languages.



Willingness to learn new skills and explore unfamiliar concepts. "The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position." We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

📌 Senior Engineer - Cmos & Metallization Test Structure Design And Layout (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque