Lead and complete advanced IC layout development for complex analog, digital, and/or mixed-signal blocks Own layout architecture decisions, including floorplanning, power routing, clocking, and signal integrity Ensure layout compliance with foundry build rules, DFM, DRC/LVS, and reliability requirements Collaborate with circuit designers to optimize performance, area, yield, and power Drive methodology improvements, layout automation, and guidelines across projects Review and sign off critical layout deliverables and achievements Mentor and technically guide layout engineers at all experience levels Partner with cross-functional teams (PD, PI, CAD, Verification, Process, Manufacturing) to resolve complex build issues Support silicon debug, failure analysis, and continuous improvement initiatives Bachelor's or Master's degree in Electrical Engineering, Microelectronics,



or related field 10+ years of experience in IC layout development for advanced semiconductor technologies Strong expertise in full‐custom layout and hierarchical build methodologies Hands‐on experience with industry‐standard EDA tools (Cadence Virtuoso or equivalent) Deep understanding of DRC, LVS, DFM, EM/IR, ESD, and reliability concepts Proven ability to lead technically complex projects with minimal supervision Excellent communication skills and ability to work across general teams Experience at advanced technology nodes (e.g., sub‐10nm, FinFET, or equivalent) Background in memory, high-speed interfaces, or high-performance logic Experience influencing layout standards, PDK feedback, or CAD flows Prior experience mentoring or serving as a technical lead or principal engineer

📌 Lead Principal Engineer, Layout Design (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque