02 ago
|
Semiconductor Engineering
|
Centro
02 ago
Semiconductor Engineering
Centro
Semiconductor Engineering is seeking a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels.
You will collaborate with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule, ensuring robust verification strategies and timely
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📌 Senior SoC Verification Engineer — UVM, Coverage & Debug (Centro)
🏢 Semiconductor Engineering
📍 Centro