CompanyQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob AreaEngineering Group, Engineering Group > ASICS EngineeringGeneral SummarySoC Design & Synthesis EngineerRole DescriptionThis role focuses on synthesizing large‐scale SoC RTL designs into high‐quality gate‐level netlists that are ready for Place & Route.
Responsibilities include owning all synthesis inputs, executing multi‐stage synthesis flows, and ensuring netlist quality with respect to timing, power, and DFT requirements prior to Physical Design handoff.The role also contributes to PPA (Power, Performance, Area) optimization by analyzing trade‐offs and recommending design or constraint improvements, while working closely with Design, DFT, and Physical Design teams to resolve issues early in the flow.
In addition, the engineer supports functional ECOs and validates post‐change correctness to improve functionality and fix late‐stage issues, ensuring timely delivery of robust, manufacturable designs used in Snapdragon products across mobile, automotive, and edge AI platforms.Required SkillsStrong understanding of RTL‐to‐gate synthesis for large SoC designsExperience with gate‐level netlist quality checks and PD‐ready handoffsSolid knowledge of timing constraints (SDC) across functional and test modesAbility to analyze and optimize PPA (Power, Performance, Area) trade‐offsExperience supporting or implementing functional ECOs and validating correctnessEffective debugging, analytical thinking, and execution under tight project schedulesMinimum QualificationsBachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design,



verification, validation, integration, or related work experience.OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.OR PhD in Science, Engineering, or related field.Preferred QualificationsMaster's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.3+ years of ASIC design, verification, validation, integration, or related work experience.2+ years of experience with architecture and design tools.2+ years of experience with scripting tools and programming languages.2+ years of experience with design verification methods.Principal Duties & ResponsibilitiesApplies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.Creates architectures, circuit specifications, logic designs, and/or system simulations based on system‐level requirements.Collaborates across teams (e.g., software architecture, hardware architecture)



to develop and execute an implementation strategy that meets system requirements and customer needs.Evaluates all aspects of process flow from high‐level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.Writes detailed technical documentation for EDA/IP/ASIC projects.Level of ResponsibilityWorks independently with minimal supervision.Decision‐making may affect work beyond immediate work group.Requires verbal and written communication skills to convey information.
May require basic negotiation, influence, tact, etc.Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).
Tasks require multiple steps which can be performed in various orders; some planning, problem‐solving, and prioritization must occur to complete the tasks effectively.EEO StatementApplicants: Qualcomm is an equal opportunity employer.
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📌 Soc Design & Synthesis Engineer (Tijuana)
🏢 Qualcomm
📍 Tijuana